Toshiba TMP87CP24AF Manual de usuario

TOSHIBATMP87CM24A/P24ACMOS 8-Bit MicrocontrollerTMP87CM24AF, TMP87CP24AFThe TMP87CM24A/P24A are the high speed and high performance 8-bit si

TOSHIBATMP87CM24A/P24A3-24-10 2002-10-03

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TOSHIBATMP87CM24A/P24AVoltage Regulator for LCD Driver in TMP87CM24A/P24AFTwo phenomenon have been found that the Voltage Regulator for LCD Driver in

TOSHIBATMP87CM24A/P24AThe phenomena (2) occurs underthe condition.Once the power supply voltage (Vdd) falls down below 2.2 V and comes back above 2.2

TOSHIBATMP87CM24A/P24AOther specification for phenomena (2) Please refer the Figure 2-57)Topr= -10 to 70 °CSymbolItem Condition Min Typ. MaxUnite)T st

TOSHIBATMP87CM24A/P24AFigure 2-56. The Diagram forthe Falling Time of Vdd3-24-105 2002-10-03

TOSHIBATMP87CM24A/P24A2.11 8-Bit AD Converter (ADC)The TMP87CM24A/P24A each have an 8-channel multiplexed-input 8-bit successive approximate

TOSHIBATMP87CM24A/P24AAD Converter Control RegisterADCCR(OOOEh)76 5432 10EOCFADSACKAINDSSAIN______1_____1_____1_____(Initial value : 0000 0000)0000 A

TOSHIBATMP87CM24A/P24A(2) Reading of AD conversion resultAfter the end of conversion, read the conversion result from the ADCDR.The EOCF is automa

TOSHIBATMP87CM24A/P24AConversionresultVAREF-VASS256Figure 2-61. Analog Input Voltage vs AD Conversion Result (typ.)3-24-109 2002-10-03

TOSHIBATMP87CM24A/P24A1.5 General-purpose Register BanksGeneral-purpose registers are mapped into addresses 0040h to OOBFh in the data me

TOSHIBATMP87CM24A/P24AInput/Output Circuitry(1) Control pinsThe input/output circuitries of the TMP87CM24A/P24A control pins are shown below.Please s

TOSHIBATMP87CM24A/P24A(2) Input/Output PortsThe input/output circuitries of the TMP87CM24A/P24A input/output ports are shown below.3-24-1112002-10-03

TOSHIBATMP87CM24A/P24AElectrical CharacteristicsAbsolute Maximum Ratings(Vss = ov )ParameterSymbol Pins Ratings UnitSupply VoltageVdd- 0.3 to 6.5VInpu

TOSHIBATMP87CM24A/P24ADC Characteristics(Vss = 0 V, Topr = - 10 to 70°C)ParameterSymbol Pins ConditionsMin Typ. MaxUnitHysteresis VoltageVhsHysteresis

TOSHIBATMP87CM24A/P24AAD Conversion Characteristics (I )(Topr= - 10to70°C)ParameterSymbol ConditionsMin Typ. MaxUnitAnalog Reference VoltageVarefVaref

TOSHIBATMP87CM24A/P24AAC Characteristics (I)(Vss = 0 V, Vdd = 4.5 to 5.5 V, Topr = - 10 to 70°C)ParameterSymbol ConditionsMin Typ. MaxUnitMachine Cycl

TOSHIBATMP87CM24A/P24ARecomended Oscillating Condition (I) (Vss = o v, VDD = 4.5to5.5 v, Topr= - ioto70°C)ParameterOsillatorFrequencyRecommenderOscill

TOSHIBATMP87PP24ACMOS 8-Bit MicrocontrollerTMP87PP24AFThe TMP87PP24A is a One-Time PROM microcontroller with low-power 384 Kbits electrical

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TOSHIBATMP87PP24APin FunctionThe TMP87PP24A has two modes: MCU and PROM.(1) MCU modeIn this mode, the TMP87PP24A is pin compatible with the TMP87CM24

TOSHIBATMP87CM24A/P24AThe TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This

TOSHIBATMP87PP24AOperational DescriptionThe following explains the TMP87PP24A hardware configuration and operation. The configuration and f

TOSHIBATMP87PP24A1.1.2 Data MemoryThe TMP87PP24A has an on-chip 2K x 8-bit data memory (static RAM).1.1.3 Input/Output Circuitry(1) Control pinsThe

TOSHIBATMP87PP24A1.2 PROM ModeThe PROM mode is activated by setting the TEST, RESET pin and the ports PI 7 to P10, P22 to P20 an

TOSHIBATMP87PP24A1.2.1 Programming Flowchart (High-speed Programming Mode)The high-speed programming mode is achieved by applying the progra

TOSHIBATMP87PP24A1.2.2 Writing Method for General-purpose PROM Program(1) AdaptersBM11127 : TMP87PP24AF(2) Adapter settingSwitch (SW1) is set to si

TOSHIBATMP87PP24AElectrical CharacteristicsAbsolute Maximum Ratings(Vss = ov )ParameterSymbol Pins Ratings UnitSupply VoltageVdd- 0.3 to 6.5VProgram V

TOSHIBATMP87PP24ADC Characteristics(Vss = 0 V, Topr = - 10 to 70°C)ParameterSymbol Pins ConditionsMin Typ. MaxUnitHysteresis VoltageVhsHysteresis inpu

TOSHIBATMP87PP24AAD Conversion Characteristics (I)(Vss = 0 V, Vdd = 2.7 to 5.5 V, Topr = - 10 to 70°C)ParameterSymbol ConditionsMin Typ. MaxUnitAnalog

TOSHIBATMP87PP24AAC Characteristics (I)(Vss = OV, Vdd = 4.5 to 5.5V, Topr = - 10 to 70°C)ParameterSymbol ConditionsMin Typ. MaxUnitMachine Cycle Timet

TOSHIBATMP87PP24ARecomended Oscillating Condition (I) (Vss = o v, VDD = 4.5to5.5 v, Topr= - ioto70°C)ParameterOsillatorFrequencyRecommenderOscillatorR

TOSHIBATMP87CM24A/P24A1.6 Program Status Word (PSW)The program status word (PSW) consists of a register bank selector (RBS) and four fl

TOSHIBATMP87PP24ADC/AC Characteristics (PROM mode) (Vss = 0 v)(1) Read OperationParameterSymbol ConditionsMin Typ. MaxUnitInput High VoltageV|H4Vcc X

TOSHIBATMP87PP24A(2) High-Speed Programming Operation (Торг = 25 ± 5°C)ParameterSymbol ConditionsMin Typ. MaxUnitInput High VoltageV|H4Vcc X 0.7-VccVI

TOSHIBATMP87PP24A3-24-1322002-10-03

TOSHIBATMP87CM24A/P24AExample: BCD operation(The A becomes 4?H after executing the following program when A = 19h, B = 28h)ADD A, B ; A<-41h, HF&

TOSHIBATMP87CM24A/P24AMSB LSB15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Stack Pointer (SP)1.7.2 Stack Pointer (SP)The stack pointer (SP) is a 16-bit

TOSHIBATMP87CM24A/P24A1.8.1 Clock GeneratorThe clock generator generates the basic clock which provides the system clocks supplied to t

TOSHIBATMP87CM24A/P24A© In the single-clock modeA divided-by-256 of high-frequency clock (fc/28) is input to the 7th stage of the divider.Do not set D

TOSHIBATMP87CM24A/P24A1/fc or 1/fs [s]Main System Clock1_StateSO SIS2S3 SO SIS2S3-------Machine cycle-------------0.5//S atfc=8MHz 122 //s at fs = 32.

TOSHIBATMP87CM24A/P24A(2) Dual-dock modeBoth high-frequency and low-frequency oscillation circuits are used in this mode. Pins P21 (XTIN

TOSHIBATMP87CM24A/P24A♦ LCD driver• Built-in voltage booster for LCD driver• With display memory (20 bytes)• LCD direct drive capability (Max 40 se

TOSHIBATMP87CM24A/P24ARESETIReset release, SoftwareSoftwareIDLE1moder :NORMALImodeSTO PI modeInterruptSTOP Din inout(a) Single-clock modeIDLE2modeSLEE

TOSHIBATMP87CM24A/P24ASystem Control Register 17 6 5SYSCR1(0038h)STOPRELM RETM OUTEN WUT_______1______(Initial value: 0000 00**)STOPRELMRETMOUTENWUT

TOSHIBATMP87CM24A/P24A1.8.4 Operating Mode Control(1) STOP mode (STORI, STOP2)STOP mode is controlled by the system control register 1 (SY

TOSHIBATMP87CM24A/P24Ab. Edge-sensitive release mode (RELM = 0)In this mode, STOP mode is released by a rising edge of the STOP pin inp

(a) STOP Mode Start (Example : Start with SET (SYSCR1). 7 instruction located at address a)Ho(/)Turn offOscillatorcircuitMainsystemclockProgramcounter

TOSHIBATMP87CM24A/P24ANote: When STOP mode is released with alow hold voltage, the following cautions must be observed. The power sup

N>O»N>OON>OUlMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimer1 1 ! 1 1 1 1 II !1 II1 1 II 1a + 2Xa + 31111SET (

TOSHIBATMP87CM24A/P24A(3) SLOW modeSLOW mode is controlled by the system control register 2 (SYSCR2) and the timer/counter 2 (TC2).a. Switching from

TOSHIBATMP87CM24A/P24Ab. Switching from SLOW mode to NORMAL2 mode First, set XEN (bit 7 in SYSCR2) to turn on the high-frequency oscillation. When tim

Ho(/)mode00>(a) Switching to the SLOW ModeN>VD o00vlnooN>owFigure 1-21. Switching between the NORMAL2 and SLOW ModesN)>N>>

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TOSHIBATMP87CM24A/P24A1.9 Interrupt ControllerThe TMP87CM24A/P24A each have a total of 14 interrupt sources: 5 externals and 9 internal

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TOSHIBATMP87CM24A/P24AExample 2 : Reads interrupt latchesLD WA, (IL)Examples: Tests an interrupt latch TEST (IL).7JR F,SSET; W<-ILh, A<-IL|_;

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TOSHIBATMP87CM24A/P24A1.9.1 Interrupt SequenceAn interrupt request is held until the interrupt is accepted or the interrupt latch is c

TOSHIBATMP87CM24A/P24AHowever, an acceptance of external interrupt 0 cannot be disabled by the EF; therefore, if disablement is necess

TOSHIBATMP87CM24A/P24ASPGeneral-purpose register save/restore using push and pop instructions:To save only a specific register, and when the

TOSHIBATMP87CM24A/P24A1.9.2 Software Interrupt (INTSW)Executing the [SWI] instruction generates a software interrupt and immediately starts

TOSHIBATMP87CM24A/P24ANotes on usage of external interrupts:Note 1: When INTO to INT5 flNTO, INTI, INT2, INT3, INT5J are used in SLOW o

TOSHIBATMP87CM24A/P24ANote 6: Change EINTCR only when IMF = 0. After changing EINTCR, interrupt latches of external interrupt inputs mu

TOSHIBATMP87CM24A/P24ABlock DiagramrI/O Port(Segment outputs)__________A___________Common outputs COM3 to COMOPower SupplyLCD drive [empower supply

TOSHIBATMP87CM24A/P24ATable 1-3. (a) External InterruptsSOURCE PinSecondaryfunctionEnableConditionEdgeDigital noise rejectrising falling bothINTO TÑÍÜ

TOSHIBATMP87CM24A/P24AExternal interrupt Control Register 1 7 6 5 4EINTCR(0037h)INTIINTO INT3INT2 INTI INT3WNC EN ES ES ES(initial value 0 0** 0 0 0

Ho(/)N>N>DD>INT3 control registerFigure1-26. (C) Bother One Edge Detictor of INT3/TC3 PinN>ooN>ow O00vlnN>>N>>

TOSHIBATMP87CM24A/P24ANotes on the usage of INT3 pin (external interrupt)1. In the case of using the INT3 pin for one edge (either rising or falling).

TOSHIBATMP87CM24A/P24AOperation description for INT3 (both-edqe interrupt) in use:1. Operation without setting/modifying external interrupt control re

TOSHIBATMP87CM24A/P24A2. Operation with setting/modifying external interrupt control register (EINTCR) after reset:1)Case3: When the initial state of

TOSHIBATMP87CM24A/P24A3)Case5: When the initial state of the INT3 pin is high after reset/low at edge switchover from rising to falling:ResetINT3ES (r

TOSHIBATMP87CM24A/P24A1.10 Watchdog Timer (WDT)The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by

TOSHIBATMP87CM24A/P24ANote: The watchdog timer consists of an internal divider and a two-stage binary counter. When clear code 4Eh is

TOSHIBATMP87CM24A/P24ATable 1-4. Watchdog Timer Detection TimeOperating mode Detection timeNORMAL1 NORMAL2 SLOW Atfc = 8MHz At fs = 32.768 kHz2^Vfc [s

TOSHIBATMP87CM24A/P24APin FunctionsPin Name Input/OutputFunctionP07 to POOI/O8-bit programmable input/output ports (tri-state).Each bit of these

TOSHIBATMP87CM24A/P24A1.10.4 Watchdog Timer ResetIf the watchdog timer output becomes active, a reset is generated, which drives the RE

TOSHIBATMP87CM24A/P24A1.11.1 External Reset InputWhen the RESET pin is held at low for at least 3 machine cycles (12/fc [s]) with the

TOSHIBATMP87CM24A/P24A2. Peripheral Hardware Functions2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)The TLCS-870 Series uses

TOSHIBATMP87CM24A/P24A2.2 I/O PortsThe TMP87CM24A/P24A have 10 parallel input/output ports (69 pins) each as follows:Primary Function Secondary Funct

TOSHIBATMP87CM24A/P24A2.2.1 Port PO (P07 to POO)Port PO is an 8-bit general-purpose input/output port which can be configured as either an input or a

TOSHIBATMP87CM24A/P24A2.2.2 PortPI (P17to P10)Port PI is an 8-bit input/output port which can be configured as an input or an output

TOSHIBATMP87CM24A/P24A2.2.3 Port P2 (P22 to P20)Port P2 is a 3-bit input/output port. It is also used as an external interrupt input,

TOSHIBATMP87CM24A/P24A2.2.4 Port P3 (P35 to P30)Port P3 is an 6-bit input/output port. When used as an input port, the output latch s

TOSHIBATMP87CM24A/P24A2.2.5 Port P4 (P47 to P40)Port P4 is an 8-bit input/output port, and is also used as an external interrupt input

TOSHIBATMP87CM24A/P24A2.2.6 Port P5 (P57 to P50)Port P5 is a general-purpose 8-bit I/O port that can be specified bitwise. It is also

TOSHIBATMP87CM24A/P24AOperational Description 1. CPU Core FunctionsThe CPU core consists of a CPU, a system clock controller, an interrupt controller,

TOSHIBATMP87CM24A/P24A2.2.7 Ports P6 (P67 to P60) Port P7 (P77 to P70) Port P8 (P87 to P80) Port P9 (P93 to P90)Port P6, P7, P8 and P9 are an 8-bit i

TOSHIBATMP87CM24A/P24ANote: The P6CR, P7CR, P8CR and P9CR are write-only register. It can not be operated by the read-modify instruction (Bit mani

TOSHIBATMP87CM24A/P24A2.3 Time Base Timer (TBT)The time-base timer is used to generate the base time for key scan and dynamic display

TOSHIBATMP87CM24A/P24ATable 2-1. Time Base Timer Interrupt FrequencyTBTCKNORMAL1/2,DLE1/2modeSLOW, SLEEP modeInterrupt FrequencyDV7CK = 0DV7CK= 1 Atfc

TOSHIBATMP87CM24A/P24AFigure 2-13. Divider Output3-24-642002-10-03

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TOSHIBATMP87CM24A/P24A2.5.2 ControlThe timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer

TOSHIBATMP87CM24A/P24A2.5.3 FunctionTimer/counter 1 has six operating modes: timer, external trigger timer, event counter, window, pulse

TOSHIBATMP87CM24A/P24ACommand startSource clockUp-counterTREG1AINTTC1 interruptSource clockUp-counterJlAllJlJlJinvrLnnnn^^0 ;XMatchCounterdetect \rr(a

TOSHIBATMP87CM24A/P24ACount startTCI pin inputInternal clock Up-counter TREG1A INTTC1iTriggerCount restart Rising edge select ^ Trigger(INT2ES = 0)---

TOSHIBATMP87CM24A/P24A1.2 Program Memory (ROM)The TMP87CM24A has a 32Kx8-bit (addresses 8000h to FFFFh), and the TMP87CP24A has a 48Kx8-bit (addresses

TOSHIBATMP87CM24A/P24A(4) Window modeCounting up is performed on the rising edge of the pulse that is the logical AND-ed product of

TOSHIBATMP87CM24A/P24AExample : Duty measurement (Resolution fc/2^ [Hz])CLR(INTTC1SW). 0 ; INTTC1 service switch initial settingLD (EINTCR),00000000B

TOSHIBATMP87CM24A/P24ACount start Count startTCI pin input Internal clock Up-counterTREG1BINTTC1iTrigger1(INT2ES = 0)JinÜinJinJtJirlU^^ ZEIXIXIXDQC

TOSHIBATMP87CM24A/P24AInternal clockUp-counterTREG1BTREG1APPG outputINTTC1TCI pin inputInternal clockUp-counterTREG1BTREG1APPG outputINTTC1Command sta

TOSHIBATMP87CM24A/P24A2.6 16-Bit Timer/Counter 2 (TC2)2.6.1 ConfigurationINTTC2interruptTimer/Counter 2 control register16-bit timer register 2TREG2H

TOSHIBATMP87CM24A/P24A2.6.3 FunctionThe timer/counter 2 has three operating modes: timer, event counter and window modes. Also timer/cou

TOSHIBATMP87CM24A/P24A(3) Window ModeIn this mode, counting up is performed on the rising edge of the pulse that is the logical AND

TOSHIBATMP87CM24A/P24A2.7.2 ControlThe timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer

TOSHIBATMP87CM24A/P24A(2) Event Counter ModeIn this mode, the TC3 pin input pulses are used for counting up. Either the rising or fa

TOSHIBATMP87CM24A/P24A2.8 8-Bit Timer/Counter 5 (TC5)2.8.1 ConfigurationFigure 2-29. Timer/Counter 5 (TC5)2.8.2 ControlThe TC5 is controlled by a t

TOSHIBATMP87CM24A/P24AExample 1 : Loads the ROM contents at the address specified by the HL register paircontents into the accumulator (TMP87CM24A :

TOSHIBATMP87CM24A/P24A2.8.3 FunctionTC5 has 3 operating modes : timer, programmable divider output, and pulse width modulation output mode.(1) Timer

TOSHIBATMP87CM24A/P24A(3) Pulse width modulation (PWM) output modePWM output with a resolution of 8-bits is possible. The internal clock

TOSHIBATMP87CM24A/P24A2.9 Serial Interface (SI01, SI02)The TMP87CM24A/P24A each have two clocked-synchronous 8-bit serial interfaces (SI01

TOSHIBATMP87CM24A/P24ASI01, SI02 Control Registers 17 6 5 4SI01CR1(0020h)SI02CR1(0022h)SIOSSIOINH,SIOM ,____________(Initial value : 0000 0000)SIO

TOSHIBATMP87CM24A/P24AMotel: Tf frame time, Tq: data transfer time^pin Un_Jn_Jn_Jn_n_nLnLrULTTfNote 2:Note 3:Note 4: Note 5: Note 6:Note 7:The low

TOSHIBATMP87CM24A/P24AExternal ClockAn external clock connected to the SCK1/SCK2 pin is used as the serial clock. In this case, the P

TOSHIBATMP87CM24A/P24A(3) Number of Words to TransferUp to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-

TOSHIBATMP87CM24A/P24AWhen an external clock is used, the data must be written to the data buffer register before shifting next data

TOSHIBATMP87CM24A/P24ASCK pin SlOFSO pin BiteXBit?tsoDH =min 3.5/fc [s] (In the NORMAL1/2, IDLE1/2 modes) = min 3.5/fs [s] (In the SLOW, SLEEP modes)F

TOSHIBATMP87CM24A/P24A(3) 8-bit Transmit/Receive ModeAfter setting the control registers to the 8-bit transmit/receive mode, write the da

TOSHIBATMP87CM24A/P24A1.4 Data Memory (RAM)The TMP87CM24A/P24A have a 2Kx 8-bit (address 0040h to 083Fh) of data memory (static RAM).

TOSHIBATMP87CM24A/P24AIf it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs

2.10 LCD DriverThe TMP87CM24A/P24A each have a driver and control circuit to directly drive the liquid crystal device (LCD). The pins

TOSHIBATMP87CM24A/P24A2.10.2 ControlThe LCD driver is controlled using the LCD control register (LCDCR). The LCD driver's display

TOSHIBATMP87CM24A/P24A(1) LCD driving methodsAs for LCD driving method, 4 types can be selected by DUTY (bit 4 to bit 2 of LCDCR).

TOSHIBATMP87CM24A/P24A(2) Frame frequencyFrame frequency (fp) is set according to driving method and base frequency as shown in the fo

TOSHIBATMP87CM24A/P24A(3) Booster circuit for LCD driverThe TMP87CM24A/P24A incorporate a booster circuit for the LCD driver (IV x 3 tim

TOSHIBATMP87CM24A/P24AТаFigure 2-47. Temperature Characteristics of Voltage Booster OutputNotice of using LCD driver(1) The falling time and fluctuat

TOSHIBATMP87CM24A/P24A2.10.3 LCD Display Operation(1) Display data settingDisplay data is stored to the display data area (assigned to add

TOSHIBATMP87CM24A/P24A2.10.4 Control Method of LCD Driver(1) Initial settingFigure 2-49 shows the flowchart of initialization.Example : To operate a 1

TOSHIBATMP87CM24A/P24ATable 2-13. Example of Display Data (1/4 Duty)No.display display dataNo.display display data06 l11011111 5 10110101©11100000110